Since the index for blocks in cache is 4 bits, there will be a total of 16 blocks in the cache.Given a 16 bit address and block size of 1 byte, address [3:0] will be used to index into the 16 blocks in cache and remaining bits address[15:4] will be used as tag bits.If each cache line is of size 64 bytes, how many sets will be present in the cache?How many address bits are needed as tag bits?Assume address size as 32 bits.What are the advantages and disadvantages?This is simple to design as memory is always up to date with respect to cache, but comes with the drawback that memory bandwidth is always consumed for writes.Write to main memory is deferred until the cache line is evicted or discarded from the cache.Write back Caches are better in terms of memory bandwidth as data is written back only when needed.The complexity comes in maintaining coherent data if there are multiple caches in system that can cache a same address, as memory may not always have latest data.What is the difference between an inclusive and exclusive cache?One advantage of exclusive cache is that the multiple levels of caches can together store more data.One advantage of inclusive cache is that in a multiprocessor system, if a cache line has to be removed from a processor’s cache, it has to be checked only in L2 cache while with exclusive caches, it has to be checked for presence in both L1 and L2 caches.Following are some of the algorithms that can be implemented for cache line replacements.This algorithm keeps track of when a cache line is used by associating age bits along with cache line and discards the least recently used one when needed.This algorithm keeps track of how often a line is accessed and decides to replace the ones that are used least number of times.In this algorithm, there is no information stored and a random line is picked when there is a need for replacement.What is the problem of cache coherency?Since the index for blocks in cache is 4 bits, there will be a total of 16 blocks in the cache.Given a 16 bit address and block size of 1 byte, address [3:0] will be used to index into the 16 blocks in cache and remaining bits address[15:4] will be used as tag bits.If each cache line is of size 64 bytes, how many sets will be present in the cache?How many address bits are needed as tag bits?Assume address size as 32 bits.What are the advantages and disadvantages?This is simple to design as memory is always up to date with respect to cache, but comes with the drawback that memory bandwidth is always consumed for writes.Write to main memory is deferred until the cache line is evicted or discarded from the cache.Write back Caches are better in terms of memory bandwidth as data is written back only when needed.The complexity comes in maintaining coherent data if there are multiple caches in system that can cache a same address, as memory may not always have latest data.What is the difference between an inclusive and exclusive cache?One advantage of exclusive cache is that the multiple levels of caches can together store more data.One advantage of inclusive cache is that in a multiprocessor system, if a cache line has to be removed from a processor’s cache, it has to be checked only in L2 cache while with exclusive caches, it has to be checked for presence in both L1 and L2 caches.Following are some of the algorithms that can be implemented for cache line replacements.This algorithm keeps track of when a cache